Applications

• Portable Instruments
• IF and Baseband Communication
• Cable Modems
• Set-Top Boxes
• Portable Test Equipment
• Computer Scanner
• Studio Cameras

Key Features

• Small Area < 3.87mm²
• Size x=2261.5µm y=1711.55µm
• Sample and Hold Input Stage
• Fully Differential (FD) Input Stage
• Internal or External References
• Power Down Mode

Key Specification

• Resolution 12 Bit
• Maximum Sampling Rate 20MSample/sec
• Supply Range between 3.0 V and 3.6 V
• Wide Junction Temperature Range from -40 °C to +125 °C
• Bandgap Reference Voltage (VBG) must be set to 1.25V or 1.875V at 3.3V Supply and with Internal References
• Common Mode Voltage (VCM) must be 1.65V at 3.3V Supply
• Negative Reference Voltage (VREFN) is VCM-(VBG*0.4) at 3.3V Supply
• Positive Reference Voltage (VREFP) is VCM+(VBG*0.4) at 3.3V Supply
• Negative and Positive Analog Input Voltage Range from 0.9V to 2.4V at 3.3V Supply
• Full Scale Range ±(VREFP-VREFN) at 3.3V Supply
• Total Power Consumption typical 380mW

Description

The Macro Cell ADC1220.C35 is a 12-bit high-speed pipelined ADC core cell with sampling rates up to 20MSamples/sec. It uses a fully differential Pipelined architecture with a first 3.5-bit stage, followed by seven 1.5-bit per stage and digital error correction to achieve improved linearity performance. A wide-band input sample-and-hold circuit is build-in to provide low-jitter, sub-sampling capability with inherent frequency down-conversion. The raw digital words are synchronized by a chain of delay stages and overlapped and processed by the digital error correction logic to produce the 12-bit digital output code.

The reference voltages are internally generated from a bandgap reference that must be supplied to the cell. A power down capability is included for very low power dissipation in stand-by mode.