Description

The AS1161 (Deserializer) transforms the high-speed LVDS serial data stream back into a 10-bit wide parallel data bus with recovered parallel clock.

The device is compliant to IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture (including the defined boundary-scan test logic and test access port consisting of Test Data Input, Test Data Out, and Test Mode Select, Test Clock, and Test Reset).

The device also features a at-speed BIST mode which allows the interconnects between the serializer a deserializer to be verified at-speed.

The single differential-pair data-path makes PCB design easier, and reduced cable/PCB-trace count and connector size significantly reduce cost. Since one output transmits clock and data bits serially, clock-to-data and data to data skew is eliminated.

Powerdown mode reduces supply current when the device is idle. The AS1161 is available in a CTBGA 49-bumps pin package

Key Features

Serial Bus LVDS Data Rate: 660 Mbps @ 66MHz Clock

10-bit Parallel Interface

Synchronization Mode and Lock Indicator

Programmable Edge Trigger on Clock

High Impedance on Rx Inputs during Poweroff

Bus LVDS Serial Output Load: 28Ω

IEEE 1149.1 (JTAG) Compliant and At-Speed BIST Test Mode

Clock Recovery from PLL Lock to Random Data Patterns

Guaranteed Transition each Data Transfer Cycle

Chipset (Tx + Rx) Power Consumption: < 500 mW @ 66MHz

Single Differential-Pair eliminates Multi-Channel Skew

Flow-Through Pinout for Simple PCB Layout

Small CTBGA 49-bumps Package

Applications

The devices are ideal for cellular phone base stations, add drop muxes, digital cross-connects. DSLAMs, networkswitches and routers or backplane interconnect.

Block diagram for AS1161 10-Bit LVDS Deserializer