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On our web site http://asic.ams.com you can find a document called "Foundry Engineering Input Document". This document contains helpful information and 3 forms which must be filled in and sent to Foundry Engineering Administration: sabine.radesey@ams.com

There are several possibilities:

• You can e-mail databases < 8Mb (compressed) to Foundry Engineering Administration: sabine.radesey@ams.com
• You can send a CDROM, DAT/DDS 4 mm or floppy disk to :
  ams (austriamicrosystems AG)
  Business Unit Full Service Foundry
  Department Foundry Engineering
  Attn: Ms. Sabine Radesey
• You can request an ftp account on our file server: Send an e-mail to peter.pann@ams.com.
  For an ftp account we need the internet name and/or IP address of your computer, any user name and any password.

Each layout must have a 5 to 8 digit number inside the chip layout. You can request that number from Foundry Engineering Administration: sabine.radesey@ams.com . You find a cell called RVBLK in the GDSII library. That cell is an example for a device number. Below the number there are revision blocks. Revision NC is a square for all levels. For a redesign e.g. on metal 1 level please change the square to an A and so on. Letters can be found in cell EXAMPLE.

Each layout needs the following special cell inside the chip border:

BUTTERFLY: That is a butterfly shaped alignment mark which is used by our mask shop. That cell must be inserted into min 3 corners of the chip.

RVBLK: Chip identification number and revision block, see question "what is a device number"

SCRIBE_EXAMPLE: That is a lower left corner of a seal ring. Insert that cell into your layout and stretch that structure around the whole chip. Make sure that the final die size is an integer multiple of 5 microns.

SCRIBE_CUT: That is an example of a seal ring interruption. This interruption is necessary e.g. for separation between analog and digital supplies.

PWR_CUT: Whenever you are using cell SCRIBE_CUT you have to insert appropriate power cut cells in order to fulfill the ESD related design rules.

In principal a layout consists of "drawn" and "derived" layers. Make sure that the final layout includes both "drawn" and "derived" layers. Attention: Generate the "derived" layers before you insert the RVBLK cell, otherwise the revision blocks would be incorrect.

No, the Standard Family Cells would generate a lot of error messages. Check a cell hierarchy below the top cell.

The "definition layers" are used by some of our DRC, ERC and LVS check programs. Whenever you order one of these services the "definition layers" must be included in the GDSII database.