説明

The AS3531 is ams' new generation SoC for portable digital audio products. Its highly flexible architecture allows single chip solutions for high performance and ultra low power audio products with minimum count of external components.

Using low power process technologies with ultra low leakage currents provides an outstanding performance in terms of power consumption and utmost integration densities for embedded on-chip RAM and ROM areas.

The AS3531 integrates a powerfull Audio Engine that enables lowest possible system clock rates for audio decoding. This audio engine supports all common audio decoding standards: MP3, AAC+ and WMA. Together with the audio postprocessor this enables devices with less than 15mW power consumption for typical audio playback use cases.

The AS3531 contains all digital functions together with the audio analog frontend (AFE) and all necessary power management blocks.

These function blocks include on-chip RAM and ROM memories, interface blocks for data transfer and storage like USB, NandFlash, MMC, SD, SDIO, CE-ATA, GPIO, SSP, clock generation and digital power optimisation functions.

ams provides a total system solution reference design including all necessary software blocks for low level HW drivers, device IO functions and a dedicated reference application with a feature rich set of audio functions.

The AS3531 contains an ultra low power stereo audio codec. It allows playback in higher than CD quality and recording in FM quality. It has a variety of audio inputs and outputs to directly connect electret microphones, 16 /32 headsets and auxiliary signal sources via a 3-channel mixer.

Further the device offers advanced power management functions. All necessary ICs and peripherals in a Digital Audio Player are supplied by the included AFE. The different regulated supply voltages are programmable via the serial control interface. The AFE also contains a Li-Ion battery charger. The single supply voltage may vary from 2.7V to 5.5V.

The AFE has an independent 32kHz real time clock (RTC) on chip which allows a complete power down of the system CPU.

主な機能

1. Basic System

• ARM926-EJ RISC Controller
  • 32/16 bit RISC architecture
  • 16-bit Thumb instruction set
  • ARMv5TEJ extended DSP instruction set and single cycle MAC
  • Memory Management Unit
  • Embedded ICE JTAG debug interface
  • 16KB Instruction + 16KB Data Cache
  • Up to 250 MHz clock speed
  • Power consumption: 0.265 mW/MHz including caches at typical conditions
  • 32/16 bit RISC architecture
• Memory
  • 512 KByte embedded SRAM connected to AHB1
  • 128 KByte ROM (128KB bootrom + 32KB GF-table)
  • 32 KByte embedded SRAM connected to AHB2 as buffer memory within AHB2 bus domain
• AMBA Bus
  • Two AHB bus segments
    • AHB1 with all Core/Memory high performance elements running up to 150 MHz
    • AHB2 with all peripheral interface blocks running at max. 100 MHz bus speed
  • AHB bus bridge between AHB1 and AHB2
    • Synchronous 1:1 mode
    • Asynchronous mode
      
  • AHB interconnect matrix for high throughput
    • AHB to APB bridge
    • Connected to AHB2
• DMA controller
  One DMA controller located in each of AHB1 and AHB2 bus domain
  • DMA1 in AHB1 bus domain
    • 8 simultaneously opened DMA channels
    • 16 DMA requests
  • DMA2 in AHB2 bus domain
    • 8 simultaneously opened DMA channels
    • 32 DMA requests
• Interrupt Controller (VIC)
  • Support for 32 non-vectored interrupts
  • Support for 32 vectored interrupts
• Timer and Watchdog
  • Two independent timer blocks (A+B) with two 32-bit counters each
  • Two timer trigger event inputs
  • Watchdog
• Chip Control Unit
  • Two independent 1 GHz PLL generators (PLLA, PLLB)
  • Internal 24 MHz oscillator
  • Optional usage of external oscillator
  • Four programmable clock outputs
  • Chip version number
  • Control of IO multiplexing
  • Universal spare registers
  • Clock gating / block enables
  • JTAG disable bit
• Keyscan Controller
  • Up to 16 keys in a 4x4 matrix
  • Low power mode
  • Interrupt generation
• IMON
  • Intelligent hardware monitor for bus and system profiling for continuous system monitoring and power optimization.
  • Very flexible selection of input events
  • Monitoring averaging or peak conditions
  • Scalable counters
  • Programmable interrupt generation
• OTP
  • 256 Bit one-time-programmable memory
  • Contains unique ID

2. Interfaces

• USB 2.0 HS & OTG Interface
  • Up to 480Mbit/s transfer speed
  • USB 2.0 HS/FS physical including OTG support
  • USB 2.0 HS/FS digital core including OTG host
  • Dedicated dual port buffer RAM
  • DMA bus master functionality
  • Total of seven endpoints (1xCONTROL, 3xIN, 3xOUT)
• NandFlash Interface
  • 8 and 16 bit flash support
  • 3, 4 & 5 byte address support
  • DMA support
  • Basic hardware ECC for SLC
  • Extended BCH error correction for MLC (correction of up to 8 errors within 512 byte)
  • Caching of ECC data for 2K/4K/8K page sizes to write ECC data to spare region
• MMC/SD Interface
  • Mobile Storage controller supporting various standards
    • SD card according to SD Phys. Layer Spec V2.0
    • SDHC card according to SD Phys. Layer Spec V2.0
    • SDIO interface according to SD spec part E1, SDIO Spec V2.0
    • Multimedia Card according to MMC Spec V4.2 including MMCplus and MMC Mobile
    • Consumer Electronics Advanced Transport Architecture (CE-ATA version 1.2)
      
  • Other Features
    • Integrated 2048 byte FiFo
    • Separate clock for bus interface and card interface
    • 1, 4 or 8 bit data width for MMC card IF
    • 1, 4 bit data width for SD card IF
    • AMBA AHB bus interface
• Synchronous Serial Interface
  • Master/slave
  • TX/RX FiFo buffering (16 byte)
  • DMA support
  • 8/16 bit support
• I²C Control Interfaces
  • Master/slave function
  • FiFo buffering (16 byte)
  • DMA support
  • Maximum 400 KHz speed
• UART
  • Baud rates up to 2 Mbit/s
  • Internal RX/TX FiFo buffering (64 byte)
  • DMA support
  • Irda SIR Encoder/Decoder
• General Purpose IO
  • Most of the PINs configurable as GPIO
  • Configurable drive strength
  • Configurable pull-down function
  • Each GPIO PIN can be used as programmable interrupt source
• Display Interface
  The DBOP (data block output port) interface is perfectly suited for all display types with μController style interfaces.
• DBOP
  • Configurable interface for different types of uController
  • System interfaces (Intel 80xx or Motorola 68xx style)
  • FiFo buffer (128x32) and DMA support
  • 8 or 16 bit modes

3. Audio Engine

• Audio Accelerator
  • Ultra low power accelerator for decoding of MP3, WMA and AAC.
  • Includes ten-band equalizer with 64 steps (-20 ÷ 20 db gain) and 32-step volume control
• MP3 features
  • 9 MHz clock frequency for MP3 decoding with 320 kbit/s input bit rate / 48 KHz audio sampling rate
  • Support MPEG-1 layer III and MPEG-2 layer III (ISO11172-3 and ISO13818-3) formats
  • Support for constant and variable bit rate from 8 to 320 kbps
• WMA features
  • WMA V8 and V9 compatible WMA decoder
  • Support of bit rates from 5kbps up to 382 kbps
• AAC features
  • AAC with support of CBR and VBR
• Audio Post-Processor
  For flexible audio signal processing an internal audio matrix is available together with a audio mixer, equalizer and sample rate converter.
  
  • 5 band graphic equalizer
  • I²SIN input sample rate conversion for audio mixing with signals running on other sampling rate
  • Audio mute
  • L/R channel swap
  • Gain attenuation
  • Limiter modes
• Security Engine
  • AES ciphering supporting 128 bit keys with ECB, CBC and CTR block cipher modes
  • DES and 3-DES ciphering supporting ECB and CBC block cipher modes
  • RC-4 ciphering supporting 40-bit and 128-bit key expansion modes
  • All cipher modes support both encrypt and decrypt operations
  • SHA-1 and MD-5 hashing algorithm with support for HMAC mode (key sizes of 1 to 64 byte)
  • Power optimized True Random Number Generator (TRNG) supporting initial seeding and 32-bit random word every 128 clock cycles

4. Extended System Features

• Boot Options
  The chip contains an on-chip ROM Bootloader that supports booting from various kinds of external flash devices. During boot, the application firmware is loaded from the external flash device into the RAM. In addition to this boot functionality, also the firmware programming and firmware update is supported.
  
  • NandFlash
  • SD/MMC/SDIO/CE-ATA
  • Bootloader concept with 1st/2nd level loader for initial firmware programming and firmware update
  • Secured firmware update mechanism
• Modes of operation
  • Normal operation
  • Hibernation mode (clock stopped)

5. Audio Frontend Features

• Audio Features
• Audio power consumption:
  • 5mW: 96dB DAC to Headphone @ 1.8V, 32
  • 7mW: 100dB DAC to Headphone @ 2.9V, 32
• Sigma Delta DAC
  • 96dB SNR ('A' weighted) @ 1.8V
  • 100dB SNR ('A' weighted) @ 2.9V
  • 8-48kHz sampling frequency
    
• Sigma Delta ADC
  • 83dB SNR ('A' weighted) @ 1.8V
  • 8-24kHz sampling frequency
    
• Microphone Input
  • 3 gain pre-setting (28dB/34dB/40dB) and AGC
  • 32 gain steps @1.5dB and MUTE
  • Supply for electret microphone
  • Microphone detection
  • Remote control by switch
• Line Input
  • Volume control via serial interface
  • 32 steps @1.5dB and MUTE
  • Stereo or 2x mono
    
• Audio Mixer
  • 6 channel input/output mixer with AGC
  • Mixes line inputs and microphones with DAC
  • Left and right channels independent
• Line Output
  • Volume control via serial interface
  • 32 steps @1.5dB and MUTE
  • 1Vp @10k
  • Ground noise cancellation
    
• High Efficiency Headphone Amplifier
  • Volume control via serial interface
  • 32 steps @1.5dB and MUTE
  • 2x12mW @16 driver capability@ 1.8V supply
  • THD -74dB @16 ; 1.8V
  • 2x40mW @16 driver capability@ 2.9V supply
  • THD -77dB @16 ; 2.9V
  • Headphone and over-current detection
  • Phantom ground eliminates large capacitors
  • Ground noise cancellation
• Power Management
  • Voltage Generation
    • Step down for CPU core (1.2V typ, 250mA)
    • Step down for peripheral (0.65V-3.4V, 250mA)
    • LDO1 for AFE audio supply (1.7V, 50mA)
    • LDO2 for AFE IO/audio supply (2.7V, 200mA)
    • LDO3 for peripherals (1.2V-3.5V, 100/200mA)
    • LDO4 for peripherals (1.2V-3.5V, 100/200mA)
    • VBUS comparator
    • Separate input for LDO3
    • Power supply supervision
    • 5sec and 10sec emergency shut-down
      
  • Backlight Driver
    • Step up for backlight (15V (25V))
    • Current control mode (1.1-36mA)
    • Voltage control mode
    • Automatic dimming
    • Over-voltage protection
  • Battery Charger
    • Automatic trickle charge (55mA)
    • Prog. constant current charging (55-460mA)
    • Prog. constant voltage charging (3.9V-4.25V)
    • Current limitation for USB mode
    • Integrated battery switch
  • General AFE Features
    • Supervisor
      • Automatic battery monitoring with interrupt generation and selectable warning level
      • Automatic temperature monitoring with interrupt generation and selectable warning and shutdown levels
        
    • Real Time Clock
      • Ultra low power 32kHz oscillator
      • 32-bit RTC sec counter, 96 days auto wake-up
      • selectable alarm (seconds or minutes)
      • 128-bit free SRAM for random settings
      • 32kHz clock output to peripheral
      • Voltage generation
      • Trimable oscillator
      • <1μA total power consumption
        
    • General Purpose ADC
      • 10-bit resolution
      • 19 inputs analog multiplexer
    • Interfaces
      • 2-wire serial control interface
      • Reset pin with selectable delay, power good pin
      • 64-bit unique ID (OTP)
      • 23 different interrupts
• Power Consumption
  Playback use case: MP3 / AAC / WMA playback 128kbit/s, 44.1 KHz, output level 150 mVrms, no external memory. Depending on output quality, following power consumption values are achieved. Standby use case: clock stopped, only voltage generation for keeping memory content is on, system will wakeup by timer interrupt
• Single chip CTBGA 124 with 0.5 mm ball pitch, 8x8 mm

ｱﾌﾟﾘｹｰｼｮﾝ

• Portable digital Audio players
  • With ultra low power consumption
  • With optional recording capability
  • With up to 16 key user interface
  • Supporting internal and external non-volatile memory
  • With colour LCD display interface
  • With support for Microsoft WMDRMv10 or other DRM systems

Block diagram for AS3531 Mobile Entertainment IC